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ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS84320-01 is a general purpose, dual output Crystal-to-3.3V Differential LVPECL High FreHiPerClockSTM quency Synthesizer and a member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. The ICS84320-01 has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 620MHz to 780MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics of the ICS84320-01 make it an ideal clock source for 10 Gigabit Ethernet, SONET, and Serial Attached SCSI applications.
FEATURES
* Dual differential 3.3V LVPECL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK * Output frequency range: 77.5MHz to 780MHz * Crystal input frequency range: 14MHz to 40MHz * VCO range: 620MHz to 780MHz * Parallel or serial interface for programming counter and output dividers * Duty cycle: 49% - 51% (N > 1) * RMS period jitter: 2ps (typical) * RMS phase jitter at 155.52MHz, using a 38.88MHz crystal (12kHz to 20MHz): 2.5ps (typical) Offset Noise Power 100Hz ................. -90.5 dBc/Hz 1kHz ............... -114.2 dBc/Hz 10kHz ............... -123.6 dBc/Hz 100kHz ............... -128.1 dBc/Hz * 3.3V supply voltage * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free RoHS (6) packages
IC S
VCO_SEL
nP_LOAD
BLOCK DIAGRAM
VCO_SEL XTAL_SEL TEST_CLK XTAL1 OSC XTAL2 0 1
PIN ASSIGNMENT
M4 M3 M2 M1 M0
32 31 30 29 28 27 26 25 M5 M6 M7 M8 N0 N1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FOUT0 nFOUT0 FOUT1 nFOUT1
TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE
XTAL1
24 23 22
XTAL2 TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR
ICS84320-01
21 20 19 18 17
PLL
PHASE DETECTOR MR /M VCO 0 1 /N /1 /2 /4 /8
nc VEE
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
CONFIGURATION INTERFACE LOGIC
TEST
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 32-Lead VFQFN 5mm x 5mm x 0.925 package body K Package Top View
REV. C OCTOBER 22, 2007
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ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The ICS84320-01 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 620MHz to 780MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84320-01 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relation-ship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M The M value and the required values of M0 through M8 are shown in Table 3B to program the VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 25 M 31. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-toLOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 0 0 1 1 T0 0 1 0 1 TEST Output LOW S_Data, Shift Register Input Output of M divider CMOS Fout
SERIAL LOADING
S_CLOCK
S_DATA
T1
T0
H
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
S
t
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N1
M, N
nP_LOAD
t
S
t
H
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
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TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3, 4, 28, 29, 30, 31, 32 5, 6 7 8, 16 9 10 11, 12 13 14, 15 Name M5 M6, M7, M8, M0, M1, M2, M3, M4 N0, N1 nc VEE TEST VCC FOUT1, nFOUT1 VCCO FOUT0, nFOUT0 Input Input Input Unused Power Output Power Output Power Output Type Pullup M divider inputs. Data latched on LOW-to-HIGH transition of Pulldown nP_LOAD input. LVCMOS / LVTTL interface levels. Pulldown Determines output divider value as defined in Table 3C, Function Table. LVCMOS / LVTTL interface levels. No connect. Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Core supply pin. Differential output for the synthesizer. LVPECL interface levels. Output supply pin. Differential output for the synthesizer. LVPECL interface levels. Active High Master Reset. When logic HIGH, forces the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between cr ystal or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. Test clock input. LVCMOS / LVTTL interface levels. Description
17
MR
Input
Pulldown
18 19 20 21 22 23 24, 25 26 27
S_CLOCK S_DATA S_LOAD VCCA XTAL_SEL TEST_CLK XTAL2, XTAL1 nP_LOAD VCO_SEL
Input Input Input Power Input Input Input Input Input
Pulldown Pulldown Pulldown
Pullup Pulldown
Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Parallel load input. Determines when data present at M8:M0 is Pulldown loaded into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. Pullup LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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TABLE 3A. PARALLEL
AND
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK X X X L L X S_DATA X X X Data Data Data X Data Reset. Forces outputs LOW. Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. X X L L L H
MR H L L L L L L L
nP_LOAD X L H H H H H
M X Data Data X X X X X
N X Data Data X X X X X
S_LOAD
NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency (MHz) 625 * 700 * M Divide 25 * 28 * 256 M8 0 * 0 * 128 M7 0 * 0 * 64 M6 0 * 0 * 32 M5 0 * 0 * 16 M4 1 * 1 * 8 M3 1 * 1 * 4 M2 0 * 1 * 2 M1 0 * 0 * 1 M0 1 * 0 * 1
775 31 0 0 0 0 1 1 1 1 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs N1 0 0 1 1 N0 0 1 0 1 N Divider Value 1 2 4 8 Output Frequency (MHz) Minimum 62 0 310 155 77.5 Maximum 780 390 195 97.5
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO (LVCMOS) Outputs, IO (LVPECL) Continuous Current Surge Current 4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO + 0.5V 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 32 Lead LQFP 47.9C/W (0 lfpm) 32 Lead VFQFN 34.8C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VCC - 0.22 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 155 22 Units V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VIH Parameter Input High Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 TEST_CLK VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, XTAL_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, XTAL_SEL, VCO_SEL VOH VOL Output High Voltage Output Low Voltage TEST; NOTE 1 TEST; NOTE 1 Test Conditions Minimum 2 2 -0.3 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 1.3 150 5 Units V V V V A A A
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
-150 2. 6 0.5
A V V
NOTE 1: Outputs terminated with 50 to VCCO/2.
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TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
Peak-to-Peak Output Voltage Swing 0.6 VSWING NOTE 1: Outputs terminated with 50 to VCCO - 2V. See "Parameter Measurement Information" section, "3.3V Output Load Test Circuit".
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter TEST_CLK; NOTE 1 fIN Input Frequency XTAL1, XTAL2; NOTE 1 Test Conditions Minimum 14 14 Typical Maximum 40 40 Units MHz MHz
S_CLOCK 50 MHz NOTE 1: For the input cr ystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 620MHz to780MHz range. Using the minimum input frequency of 14MHz, valid values of M are 45 M 55. Using the maximum frequency of 40MHz, valid values of M are 16 M 19.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 14 Test Conditions Minimum Typical Maximum 40 50 7 1 Units MHz pF mW Fundamental
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter FOUT t jit(per) t jit t sk(o) tR / tF tS Output Frequency Period Jitter, RMS; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Skew; NOTE 2, 3 Output Rise/Fall Time M, N to nP_LOAD Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD o dc tPW Output Duty Cycle Output Pulse Width N>1 fOUT 625 > 625 fOUT > 100MHz 155.52MHz, 12kHz - 20MHz 20% to 80% 150 5 5 5 5 5 5 49 45 tPERIOD/2 - 150 51 55 tPERIOD/2 + 150 1 Test Conditions Minimum 77.5 2.0 2.5 15 600 Typical Maximum 780 2.6 Units MHz ps ps ps ps ns ns ns ns ns ns % % ps ms
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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TYPICAL PHASE NOISE AT 155.52MHZ
-10 -20 -30 -40 -50 -60
OC-48 Sonet Bandpass Filter 155.52MHz
RMS Phase Jitter (Random) 12kHz to 20MHz = 2.5ps (typical)
0
NOISE POWER dBc Hz
-70 -80 -90 -100 -110 -120 -130 -150 -160 -170 -180 1 10 100 1k 10k 100k 1M 10M 100M -140
Raw Phase Noise Data
Phase Noise Result by adding Sonet Bandpass Filter to raw data OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 622.08MHZ
-10 -20 -30 -40 -50 -60
OC-48 Sonet Bandpass Filter 622.08MHz
RMS Phase Jitter (Random) 12kHz to 20MHz = 2.48ps (typical)
0
NOISE POWER dBc Hz
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 1 10 100
Raw Phase Noise Data
Phase Noise Result by adding Sonet Bandpass Filter to raw data
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION
2V 2V nFOUTx VCC, VCCO
Qx
SCOPE
FOUTx nFOUTy
VCCA
LVPECL
VEE
nQx
FOUTy
tsk(o)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
VOH VREF VOL
nFOUTx FOUTx
Pulse Width t
PERIOD
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
odc =
Histogram
t PW t PERIOD
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84320-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 24 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. The 24 resistor can also be replaced by a ferrite bead.
3.3V VCC .01F VCCA .01F 10F 24
FIGURE 2. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. TEST_CLK INPUT For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode operation. The ICS84320-01 has a built-in crystal oscillator circuit. This interface can accept either a series or parallel crystal without additional components and generate frequencies with accuracy suitable for most applications. Additional accuracy can be achieved by adding two small capacitors C1 and C2 as shown in Figure 3.
25 C1 18p X1 18pF Parallel Crystal 24 C2 22p
XTAL1
XTAL2 ICS84320-01
FIGURE 3. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 4. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the
VDD
series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
R1 Ro Rs 50 0.1f XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
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TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
Zo = 50
125
3.3V 125
FOUT
FIN
Zo = 50
Zo = 50
FOUT FIN
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
50 VCC - 2V RTT
84 84 Zo = 50
RTT =
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
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LAYOUT GUIDELINE
The schematic of the ICS84320-01 layout example used in this layout guideline is shown in Figure 6A. The ICS8432001 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board.
C1 X1 32 31 30 29 28 27 26 25
C2
U1
9 10 11 12 VCC 13 FOUT 14 FOUTN 15 16
ICS84320-01
TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE
1 2 3 4 5 6 7 8
M4 M3 M2 M1 M0 VCO_SEL nP_LOAD XTAL1
VCC 24 23 22 21 20 19 18 17 R7 24 VCCA S_LOAD S_DATA S_CLOCK C11 0.01u C16 10u
M5 M6 M7 M8 N0 N1 nc VEE
XTAL2 T_CLK nXTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR
REF_IN XTAL_SEL
VCC
VCC
R1 125 Zo = 50 Ohm IN+ TL1
R3 125
C14 0.1u C15 0.1u Zo = 50 Ohm
+ IN-
TL2 R2 84 R4 84
-
FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. * The differential 50 output traces should have the same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible.
POWER
AND
GROUNDING
Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins 25 (XTAL1) and 24 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
X1
C1 C2
GND VCC VIA
U1
PIN 1
C11 C16 VCCA R7
Close to the input pins of the receiver
C14
TL1N
C15
TL1
R1
R2
TL1
TL1N
TL1, TL21N are 50 Ohm traces and equal length
R3
R4
FIGURE 6B. PCB BOARD LAYOUT FOR ICS84320-01
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 7. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/ electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
FIGURE 7. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE)
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84320-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84320-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.08mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 537.1mW + 60mW = 597.1mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 8A below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.597W * 42.1C/W = 95.1C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 8A. THERMAL RESISTANCE JA FOR 32-PIN LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 8B. THERMAL RESISTANCE JA FOR 32-PIN VFQFN FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
84320AY-01
34.8C/W
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ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50) * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 9A. JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 9B. JAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W
TRANSISTOR COUNT
The transistor count for ICS84320-01 is: 3776
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 10A. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - 32 LEAD K PACKAGE
S eating Plan e Ind ex Area N Anvil Singula tion A1 A3 L
(Ref.)
(N -1)x e
(R ef.)
N &N Even N 1 2
e (Ty p.) 2 If N & N
are Even (N -1)x e
OR
To p View
E2
E2 2
(Re f.)
b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C
(Ref.)
e D2 2 D2
N &N Odd
Th er mal Ba se
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 10B below.
TABLE 10B. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 1.25 0.30 1.25 5.0 3.25 0.50 0.18 0.50 BASIC 8 8 5.0 3.25 0.80 0 0.25 Reference 0.30 Minimum 32 1.0 0.05 Maximum
Reference Document: JEDEC Publication 95, MO-220
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number ICS84320AY-01 ICS84320AY-01T ICS84320AY-01LN ICS84320AY-01LNT ICS84320AK-01 ICS84320AK-01T ICS84320AK-01LF Marking ICS84320AY-01 ICS84320AY-01 ICS84320A01N ICS84320A01N ICS84320AK01 ICS84320AK01 ICS4320A01L Package 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead-Free/Annealed" LQFP 32 Lead "Lead-Free/Annealed" LQFP 32 Lead VFQFN 32 Lead VFQFN 32 Lead "Lead-Free" VFQFN Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel tray 2500 tape & reel tray Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
ICS84320AK-01LFT ICS4320A01L 32 Lead "Lead-Free" VFQFN 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" or LN" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 84320AY -01
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780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET Rev A A T11 T4A T6 B Table Page 7 16 1 5 6 8 9 10 18 6 14 - 15 14 19 Description of Change Updated Typical Phase Noise plots and format. Ordering Information Table - added Lead Free Par t/Order Number. Features Section - added Lead-Free bullet. Power Supply DC Characteristics - updated VCCA min. from 3.135V to VCC - 0.22. Crystal Characteristics Table - added Drive Level. Corrected 3.3V Output Load AC Test Circuit diagram. Added Recommendations for Unused Input and Output Pins. Added LVCMOS to XTAL Interface. Ordering Information Table - added lead-free par t number. Added VFQFN package throughout the datasheet. LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to VCCO - 0.9V. Power Considerations - corrected power dissipation to reflect VOH max in Table 4C. Added VFQFN EPAD Thermal Release Path section. Ordering Information Table - added lead-free marking. Date 7/2/04 8/24/04
4/14/06
T11 T4C C
4/10/07
C
T11
10/22/07
84320AY-01
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REV. C OCTOBER 22, 2007

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